The present invention relates to DC/DC converters and their use in electronic systems. More particularly, the present invention relates to reducing the initial set-point error of a DC/DC converter and expanding the margining window for electronic devices tested when powered by DC/DC converters.
Direct current-to-direct current (DC/DC) converters are commonly used in electronic devices and systems. The principal function of a DC/DC converter is to translate a readily available voltage source to an output voltage required by a specific load. For example, in a communications application, a telephone central office battery supply voltage of 48 volts may be converted to 3.3 volts for powering a conventional integrated circuit.
FIG. 1 shows a common DC/DC converter 10 that translates a DC input voltage VIN into a DC output voltage VOUT, which has a voltage level that is less than the voltage level of the input voltage VIN. This type of DC/DC converter is commonly referred to in the art as a xe2x80x9cbuckxe2x80x9d converter. The DC input voltage VIN supplied to buck converter 10 is periodically coupled to an inductor 102 and a diode 104, by operation of a switching transistor 100. Inductor 102 is also connected to a capacitor 106 and a load 108. Switching transistor 100 is controlled by a pulse width modulator (PWM) 110, which provides an alternating control signal to the gate of switching transistor 100. This alternating control signal alternately turns switching transistor 100 on and off, thereby alternately coupling and decoupling the input voltage VIN to and from converter 10.
When switching transistor 100 is turned on by the alternating control signal, current from the source of input voltage VIN is directed toward inductor 102 and diode 104. Due to the orientation of diode 104, however, the current is blocked from passing to ground and, instead, flows and increases linearly through inductor 102 to charge capacitor 106 and power load 108. When transistor switch 100 is turned off by the alternating control signal, VIN is decoupled from inductor 102 and diode 104. However, the current through inductor 102 continues to flow, since current through an inductor cannot decrease instantaneously to zero. Because of the decoupling of VIN from the converter, however, the inductor current does decrease, albeit at a linear fashion, flowing through the loop formed by inductor 102, the parallel combination of capacitor 106 and load 108, and diode 104. The alternate coupling of VIN to and from converter 10 results in an inductor current that is triangular in shape. The triangular-shaped inductor current is filtered by the combination of inductor 102 and capacitor 106 to remove the triangular shape and thereby provide the intended flat DC output voltage VOUT.
As might be expected, the voltage level of DC output voltage VOUT depends on how long switching transistor 100 is turned on compared to how long it is turned off. In fact, it can be shown that the average voltage level of VOUT for a converter, like the one shown in FIG. 1, is directly proportional to the duty cycle of the alternating control signal, which controls the on/off time of switching transistor 100. (The duty cycle D of a periodic waveform is the fraction of the period of the waveform during which the waveform is high.)
The voltage level of DC output voltage VOUT is dynamically monitored and adjusted in the converter 10 to encourage the voltage level of DC output voltage VOUT to be constant over time. As shown in FIG. 1, this is typically carried out by coupling VOUT to an error amplifier 112, via a voltage divider comprising a first resistor 114 and a second resistor 116, and comparing it to a reference voltage VREF. Accordingly, when the voltage at node 118 falls below VREF, indicating that VOUT is too low, error amplifier 112 provides an error signal to PWM 110 causing PWM 110 to increase the duty cycle D of the alternating control signal. On the other hand, when the voltage at node 118 rises above VREF, indicating that VOUT is too high, error amplifier 112 provides an error signal to PWM 110 causing PWM 110 to decrease the duty cycle D of the alternating control signal.
Ideally, the buck converter 10 in FIG. 1 provides an output voltage VOUT that is immune to changes in load conditions, has no AC component and maintains a constant DC level over time. In practice, however, a DC/DC converter does not provide these desirable attributes, as various internal and external factors affect the accuracy of the output. Performance limitations attributable to these factors are often characterized and published in a data sheet accompanying the converter. One of these performance limitations is characterized and expressed as the error in the xe2x80x9cinitial set-pointxe2x80x9d. The initial set-point is the intended or designed output voltage level of a given DC/DC converter design under specified load conditions. The actual output voltage level may, and often does, differ from the initial set-point, due to inaccuracies of components used to build the converter. In particular, in the DC/DC converter 10 shown in FIG. 1, the voltage divider formed by resistors 114 and 116 provides a divided voltage that differs from an intended voltage due to inaccuracies in the resistances of the resistors forming the voltage divider. Additionally, in the same design, the actual output voltage level of one converter often differs from the actual output voltage of another due to deviations in intended resistance values of the resistors used in one converter compared to the next. Other factors that contribute to the initial set-point error include variations in the reference voltage VREF, the inability of error amplifier 112 to maintain its intended output voltage under different input voltages (line regulation) and output currents (load regulation). The guaranteed maximum range of variation between the intended output voltage and the initial set-point is normally published in an accompanying data sheet and is referred to as the xe2x80x9cinitial set-point error.xe2x80x9d A typical initial set-point error is +/xe2x88x922-3%.
DC/DC converters are often employed to supply power to a system comprised of integrated circuits and other electrical and electronic components. A system is designed so that it is guaranteed to function properly when powered within a tolerable supply range defined by upper and lower supply limits (or xe2x80x9cmarginsxe2x80x9d). To ensure that the system does in fact function properly within the tolerable supply range, xe2x80x9cmarginingxe2x80x9d tests are typically performed to test the functionality of components of the system when powered at these supply range margins. The margining tests allow a tester to isolate and screen out those components that malfunction when the system is powered at the supply margins.
A typical margining test set-up 20 for performing margining tests is shown in FIG. 2. A tester 200, as controlled by a workstation 202, is programmed to provide test input vectors 204 to a device under test (DUT) 206, which is assumed here to be a digital device (e.g. an ASIC) for purposes of example. Test input vectors 204 typically comprise a predetermined pattern of digital bits, which are sent to DUT 206. DUT 206 operates on test input vectors 204 and provides one or more test result vectors 208. Tester 200 is configured to receive test result vectors 208 from DUT 206 and compare them to a set of expected results. A DC/DC converter 210, which supplies power to test set-up 20, includes an output terminal VOUT, which supplies a DC output voltage, a ground terminal GND, which is coupled to ground, and a trim input TRIM. As shown in FIG. 2, testing the functionality of DUT 206 at the supply margins is typically performed by coupling a first end of a trim resistor 212, having a resistance value specified by the converter data sheet, to trim input TRIM and coupling a second end of trim resistor 212 alternately, between the GND and VOUT terminals of the converter. Tester 200 provides a control signal to a switch 214, which switches the second end of trim resistor 212 to either the GND or VOUT terminals.
An electronic component of a given system is usually designed to function properly when powered within a specific design range. So, ideally, the margins of the supply voltages supplied to the component by a converter during the margining tests would match these limits. Unfortunately, due to the initial set-point error of a converter (describe above), the margining window must be reduced to take the uncertainty in supply voltage into account. For example, even though a supply range of +/xe2x88x925% for a given system component may be specified as being acceptable, the supply margins of a converter supplying power to the component during the margining tests may have to be set to +/xe2x88x923%, in order to take into account the initial set-point error of the converter. Having to factor in the initial set-point error is undesirable since it does not ensure that components are margin tested at the true margins of their acceptable supply ranges. This is problematic as it can lead to the passing of marginal components that would otherwise fail if tested while powered at the true margins.
The initial set-point error of a DC/DC converter becomes even more problematic as the tolerance of the supply voltages of load devices is reduced. A few years ago, integrated circuits powered by a 3.3-volt supply were common. However, as transistor dimensions have been shrunk, integrated circuit designs requiring supply voltages of only 1.2-volts have become common. The lower supply designs have led to a reduction in the tolerance of supply voltage levels. For example, whereas a 3.3-volt device may be specified to tolerate variations in supply voltage of +/xe2x88x925%, a 1.2-volt device may be specified to tolerate only a +/xe2x88x923% variation in supply voltage. Consequently, as systems are designed to be powered by lower supply voltages, the initial set-point error of a DC/DC converter becomes even more of a concern.
A 3.3-volt device and a 1.2-volt device may also be specified to have the same voltage supply-tolerance percentage, e.g. +/xe2x88x925%. The initial set-point error of a 3.3-volt device and a 1.2-volt device may also be the same, say +/xe2x88x922.5%. A +/xe2x88x922.5% initial set-point error leaves a remaining +/xe2x88x922.5% to cover other variables such as voltage drops on the printed circuit board upon which the device is mounted, noise and ripple, dynamic response due to load changes, etc. However, whereas this xe2x80x9cleft-overxe2x80x9d power supply percentage (i.e. +/xe2x88x922.5%) is the same for the 3.3-volt and 1.2-volt devices, the actual left-over voltage is different for the two devices. In other words, whereas +/xe2x88x922.5% of 3.3 V leaves 82.5 mV of left-over voltage for the 3.3-volt device, +/xe2x88x922.5% of 1.2 V leaves only 30 mV of left-over voltage for the 1.2-volt device. Hence, the initial set-point error of a DC/DC converter can also make system design more challenging, particularly for devices that operate at lower voltage levels.
In addition to the foregoing, endeavoring to maintain a DC/DC converter supply voltage within a smaller tolerance window is exacerbated by increased current demands of today""s integrated circuits. State-of-the-art integrated circuits typically switch faster than older designs and, therefore, draw more current. For example, whereas a 3.3-volt integrated circuit might draw 20 A of current, a functionally equivalent 1.2-volt circuit might draw over 60 A. Larger currents make it more difficult to distribute power to the integrated circuit, since line drops between the converter and the integrated circuit are more substantial and changes in load conditions are more dramatic. Consequently, inaccuracies in the supply voltage due to increased current demands leaves even less room for acceptable error in the initial set-point of the supplying DC/DC converter.
The present invention is directed at methods and apparatus that significantly reduces the initial set-point error and improves the voltage margining accuracy of a DC/DC converter.
According to an aspect of the present invention, an apparatus for reducing the initial set-point error of a DC/DC converter comprises a DC/DC converter configured to provide a supply voltage to power terminals of a load. The converter includes a trim input for adjusting the voltage level of the supply voltage and remote sense lines coupled to power terminals of the load. A power supply controller is coupled to the remote sense lines and provides an output, which is coupled to the trim input of the converter. A voltage sensed by the remote sense lines is compared to a precision voltage reference in the power supply controller to provide an output voltage at the output of the power supply controller.
According to another aspect of the present invention, a method of reducing the initial set-point error of a DC/DC converter comprises the steps of providing a DC/DC converter configured to supply a voltage to a load, sensing a voltage actually applied to the load using sense lines of said DC/DC converter, comparing the voltage actually applied to the load to a precision voltage reference, and adjusting the voltage supplied to the load by an amount depending on the difference between the voltage actually applied to the load and the precision voltage reference.
According to another aspect of the present invention, a test set-up for performing voltage supply margining tests on a device under test (DUT) comprises a DC/DC converter configured to supply a voltage to power terminals of the DUT. The converter has a trim input and remote sense lines coupled to the DUT power terminals. A power supply controller has inputs terminals coupled to the remote sense lines and an output coupled to the trim input of the converter. Finally, a tester is coupled to the DUT and operates to compare a measured response of the DUT to an expected response. According to this exemplary embodiment, the test set-up may be configured to compare the measured response to the expected response when the voltage level of the voltage supplied to the power terminals of the DUT is approximately equal to a margin voltage of an acceptable supply voltage range of the DUT. Testing may also be performed while the voltage supplied to the DUT power terminals is within the acceptable supply voltage range of the DUT.
According to another aspect of the present invention, a method of performing voltage supply margining tests on a device under test (DUT) comprises providing a DC/DC converter configured to supply a voltage to the DUT, sensing a voltage actually applied to the DUT using sense lines of said DC/DC converter, comparing the voltage actually applied to the DUT to a precision voltage reference, adjusting the voltage supplied to the DUT by an amount depending on the difference between the sensed voltage and the precision voltage reference, and comparing a measured response of the DUT to an expected response. According to this exemplary embodiment, the power supply controller may compare the voltage sensed by the remote sense lines to the selected precision voltage reference and provide a voltage at the output of the power supply controller that causes the converter to provide a margin voltage of an acceptable supply voltage range of the DUT to the DUT.
According to another aspect of the invention, a power supply controller for reducing the initial set-point error of a DC/DC converter having remote sense lines, trim circuitry with a trim input, and power terminals for coupling to one or more electronic devices, comprises an amplifier having a first input for coupling to a signal representative of the output voltage supplied by the DC/DC converter and an output for coupling to a trim input of the DC/DC converter, and a precision voltage reference device coupled to a second input of the amplifier.
According to yet another aspect of the invention, a test set-up for performing voltage supply margining tests on a device under test (DUT) including circuitry for reducing the initial set-point error of a DC/DC converter comprises an amplifier having a first input for coupling to a signal representative of the output voltage supplied by the DC/DC converter and an output for coupling to a trim input of the DC/DC converter, a precision voltage reference for coupling to a second input of the amplifier, and a tester coupled to the DUT operable to compare a measured response of the DUT to an expected response.
Other aspects of the inventions are described and claimed below, and a further understanding of the nature and advantages of the inventions may be realized by reference to the remaining portions of the specification and the attached drawings.